1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) and a method of fabricating the same, and more particularly, to an LCD and a method of fabricating the same having storage capacitors with a high aperture ratio.
2. Discussion of the Related Art
An LCD is fabricated through a process including the steps of preparing a lower substrate on which gate lines, data lines, pixel electrodes, and switching elements, such as thin film transistors, for controlling the electric field applied to the pixel electrode are arranged in the form of a matrix; preparing an upper substrate on which a common electrode and color filters are formed; injecting a liquid crystal between the upper and lower substrates and sealing it to thereby bond the two substrates; forming polarizing plates on the outer surfaces of the two substrates; mounting a driving circuit chip on the lower substrate; and installing a back light on one of the polarizing plates.
Conventionally, the gate lines and the data lines intersect each other to form a pixel array on the lower substrate in the form of a matrix. Each pixel includes a thin film transistor connected to adjacent gate and data lines and a pixel electrode connected to one of the electrodes of the thin film transistor.
An aperture ratio is the ratio of an area where light is transmitted with respect to the entire pixel area. The picture quality of the LCD depends on the aperture ratio. Therefore, it is desirable to increase the aperture ratio by increasing the area of the pixel area where light is transmitted. However, more than 50% of the consumption power required to drive the LCD is generated by the back light. Thus, an LCD structure that has a higher aperture ratio can also reduce the power consumed by the back light.
FIG. 1 is a plan view of a conventional LCD. FIG. 1 shows one pixel region defined by a gate line 13L and data line 15L which cross or intersect each other. Referring to FIG. 1, a gate electrode 13G is connected to gate line 13L. An active layer 11 traverses gate electrode 13G. A source region 11S is formed in a portion of active region 11 at one side of gate electrode 13G, and a drain region 13D is formed at a portion of active region 11 at the other side of the gate electrode. Source region 11S is connected to data line 15L, and drain region 11D is connected to a pixel electrode 17, which covers the overall pixel region. Thus, a data signal applied through data line 15L reaches pixel electrode 17 through source and drain regions 11S, 11D.
A storage capacitor is formed near the center of the pixel. A first storage electrode 21 and active layer 11 are formed of the same material at the same layer level. A second storage electrode 22 and gate line 13L are formed of the same material at the same layer level. The second storage electrode 22 is superposed on the first storage electrode 21.
FIG. 2 is a cross-sectional view taken along line I--I of FIG. 1. Referring to FIG. 2, the active layer 11 and the first storage electrode 21 are formed of the same material on a glass substrate 10, and a gate insulating layer 12 is formed thereon. The gate electrode 13G and the second storage electrode 22 are formed of the same material on gate insulating layer 12. The gate electrode 13G defines a channel region 11C in active layer 11, and the second storage electrode 22 is superposed on the first storage electrode 21. Moreover, a first interlevel insulating layer 14 is formed on the overall surface of the substrate. Data line 15L is formed on the first interlevel insulating layer 14 to be connected to source region 11S through a contact hole formed in predetermined portions of the gate insulating layer 12 and the first interlevel insulating layer 14.
A second interlevel insulating layer 16 is formed on the overall surface of the substrate. Pixel electrode 17 is formed on the second interlevel insulating layer 16 to be connected to drain region 11D through a contact hole formed in predetermined portions of gate insulating layer 12 and the first and second interlevel insulating layers 14, 16. FIG. 2 shows a cross-section of the storage capacitor including the first storage electrode 21, the gate insulating layer 12, and the second storage electrode 22.
In the aforementioned conventional LCD, the second storage electrode is formed of a metal through which light cannot be transmitted, and is disposed near the center of the pixel region, sacrificing the aperture ratio of the pixel.
FIG. 3 is a plan view of another conventional LCD. FIG. 3 shows one pixel region defined by a gate line 13L and a data line 15L, which cross each other. Referring to FIG. 3, gate electrode 13G is connected to gate line 13L. Active layer 11 traverses the gate electrode 13G. Source region 11S is formed in a portion of active region 11 on one side of gate electrode 13G. Drain region 11D is formed in a portion of active region 11 on the other side of the gate electrode. The source region 11S is connected to date line 15L, and the drain region 11D is connected to pixel electrode 22, which covers the overall pixel region. Thus, a data signal applied through data line 11L reaches pixel electrode 22 through source and drain regions 11S, 11D.
The storage capacitor is formed over the overall pixel region, except drain region 11D. A first storage electrode 21 is formed of a transparent conductive material, such as Indium Tin Oxide (ITO). Pixel electrode 22 superposed on the first storage electrode 21 is used as a second storage electrode. In this example, the aperture ratio of this LCD is much higher than that of the above-described LCD, because the electrodes of the storage capacitor are formed of transparent conductive material. An opening exposing drain region 11D is formed in a predetermined portion of the first storage electrode 21 to allow the drain region 11D to be connected with the pixel electrode 22 placed over the first storage electrode 21.
FIG. 4 is a cross-sectional view taken along line III--III of FIG. 3. Referring to FIG. 4, active layer 11 is formed on a glass substrate 10, and a gate insulating layer 12 is formed thereon. Gate electrode 13G and gate line 13L are formed on the gate insulating layer 12, and the first interlevel insulating layer 14 is formed thereon. The gate electrode 13G defines a channel region 11C in active layer 11. Data line 15L is formed on the first interlevel insulating layer 14 to be connected to source region 11S through a contact hole formed in predetermined portions of the gate insulating layer 12 and the first interlevel insulating layer 14. A second interlevel insulating layer 16 is formed on the overall surface of the substrate. A first storage electrode 21 is formed of a transparent conductive material on the second interlevel insulating layer 16. Here, the first storage electrode 21 is not superposed on the drain region 11D and has an opening surrounding the drain region 11D, as described above.
Thereafter, a third interlevel insulating layer 18 is formed on the second interlevel insulating layer 16. A pixel electrode 22 is formed on the third interlevel insulating layer 18 to be connected to drain region 11D through a contact hole formed in predetermined portions of gate insulating layer 12, the first, second, and third interlevel insulating layers 14, 16, 18. FIG. 4 shows the cross-section of the storage capacitor including the first storage electrode 21, the third interlevel insulating layer 18, and the second storage electrode 22.
The aperture ratio of this LCD is much higher than that of the above-described LCD, as seen from FIG. 3, because the electrodes of the storage capacitor are formed of a transparent material. However, this LCD structure requires an extra third interlevel insulating layer and an extra first storage electrode. Thus, additional deposition and photolithography processes are necessary. These processes are complicated and difficult to perform, thereby resulting in poor production yield.